Simon Davidmann – Curriculum Vitae – April 2004

Summary

Nationality: British, Born: London, 1956, Married: 2 Children, Home: Oxfordshire, UK

A serial technology entrepreneur who in the last 15 years has been involved with 5 US based EDA start-up companies that have all been very successfully acquired. In each case Simon was the first employee or founder in Europe and developed and established the business.The most recent was Co-Design Automation, Inc – which he co-founded in 1998, managed as President, CEO and Chairman, and very successfully sold to Synopsys, Inc., for $36M in mid 2002.

Each start-up company Simon has been involved with has been at the cutting edge of advanced Electronic Design Automation (EDA) software. It is EDA software tools that enable the development of large silicon Integrated Circuits and Systems-on-Chips. EDA is the technology that leading chip designers use – it is technology for technologists.

Having started in the late 70’s as an EDA researcher at Essex and Brunel Universities in the UK Simon moved to the US to sell the HILO simulation software he developed at Brunel.

Returning to the UK in 1983 he became Technical Director of Simmons Electronics Ltd., a small electronics company pioneering electronic percussion where he gained experience in embedded Real Time Software development, Integrated Circuit design, Printed Circuit Board design and product manufacturing.

In 1988 Simon became the first European employee of Gateway Design Automation, Inc., the US developers of Verilog, and as the company grew managed the technical resources in Europe. After the merger with Cadence Design Systems, Inc. – the largest global EDA company, Simon assisted in the setting up of the EuCAD consulting group which pioneered the service business model in EDA. Simon was the Business Development manager specifying and managing projects and selling the services across Europe.

During 1993 Simon became Vice President and General Manager of the European operations of Chronologic Simulation, Inc. – the developers of VCS – the leading Verilog simulator of the 90’s. (Verilog is the language of chip designers.) This role involved setting up a new business in a new territory (Europe) and selling and supporting the products. Chronologic was acquired by Viewlogic, Inc, and VCS is now owned & marketed by Synopsys, Inc.

In 1995 he set up the European operations for Virtual Chips, Inc., a pioneer in the re-useable silicon Intellectual Property business and helped develop that business area by forming the US based RAPID industry organisation to promote the silicon IP business. Virtual Chips was acquired by Phoenix Technologies Ltd, and was then spun out as the Nasdaq public company inSilicon, Inc.

In 1997 Simon joined Ambit Design Systems, Inc, the inventor of timing driven digital synthesis technology and set up the European operations as VP/GM. Simon was the most successful sales person, and Europe was the most successful region worldwide. Ambit was sold to Cadence Designs Systems, Inc in 1998 for $280M.

Simon then co-founded Co-Design Automation, Inc, and spent the next 4 years as CEO growing the US based company, and commuting between Silicon Valley and Oxfordshire, UK. The company had staff in East/West US and a UK subsidiary in Oxfordshire. The focus of the company was to become a leading provider in simulation solutions for design and verification and to develop the first ‘next generation’ Hardware Design and Verification Language (HDVL) and to see it proliferated. Co-Design succeeded in accomplishing this and after getting Accellera to adopt SUPERLOG as their new language standard: SystemVerilog 3.0 it gained many large and important design wins with key customers and developed relationships with System Design and platform partners such as ARM. Co-Design was acquired by Synopsys, Inc. in Sept 2002. Simon co-authored the definitive book on SystemVerilog.

Having been involved with many of the key developments in the Design and Verification segments of EDA, and having personal experience of complex embedded systems development, Simon has an excellent understanding of the processes and methodologies involved in System-on-Chip Design and Verification.

While working in Europe for US companies, and in managing a US company from the UK, Simon has gained significant understanding of what it takes to start a company, manage it as it grows, and manage it across different sites and cultures.

Simon is on the board of directors of 2 private UK EDA companies, is a consultant to several others, and is a Visiting Professor at the Centre for Digital Music, Queen Mary, University of London.

Simon is a collector of old radios, owns two 1930’s racing cars, and is working on building up a vintage guitar collection. He has participated in two London Triathlons and runs/cycles when he can find the time.

Summary of Activities and Employment

2002 - 2003 Synopsys, Inc. Vice President Business Development, Verification Technology Group – responsible for developing European verification business.

1998-2002 Co-Design Automation, Inc. Co-Founder, President, Chairman, CEO. Co-Architecting the SUPERLOG language as a superset of Verilog and by working with Accellera made Superlog into the new Accellera SystemVerilog 3.0 standard. Developed the business plan, raised 3 rounds of funding, built the team, managed all aspects of the company, and successfully sold the company in Sept 2002.

1997-1998. Ambit Design Systems, Inc. Vice President and European General Manager. Set-up and developed European operations to market, sell, and support new generation of synthesis products. Hired staff and distributors across Europe and made Europe the most successful worldwide region. Ambit was sold to Cadence in 1998 for $280M.

1995-1997. RaviCAD, Virtual Chips, Inc. Vice President and European General Manager. Set-up and developed European. Helped develop business model of soft silicon Intellectual Property (IP) as a business. Hired staff and distributors, developed local marketing, sold and supported products. Virtual Chips was sold to Phoenix Technologies, Inc. in 1997.

1993-1995 Chronologic Simulation, Inc. Vice President and European General Manager. Set-up and developed European operations of EDA software simulation developer to market, sell, and support the new VCS product. Hired staff and worked across Europe with distributors. Chronologic was sold to Viewlogic in 1995 which was subsequently acquired by Synopsys. Inc.

1991-1993 – European CAD Developments Ltd (EuCAD) part of Cadence Design Systems, Inc. – Business Development Manager for consulting service group. Helped build new business model of EDA consulting. Developed and sold complex design/verification project plans to customers, hired consultants, and managed projects.

1988-1991 – Gateway Design Automation, Inc, Cadence Design Systems, Inc. European Technical Manager. Opened first Gateway European Office, hired staff, supported the Verilog simulation based products across Europe and following the acquisition by Cadence, worked in US on product development.

1984-1988 – Simmons Electronics, Ltd. Technical Director. Built new engineering department to develop new generation of processor based electronic percussion instruments for performing musicians. Developed products that included multi-microprocessors, real time embedded software, and digital ASIC design.

1980-1984 – Brunel University, UK - Research Fellow. As part of small team developed HILO – the first RTL simulation system. GenRad acquired marketing rights and in 1983 went to US to sell and support HILO.

1975-1980 – Essex University, UK – MSc, and BSc in EE.

1994-1998 – Kings College London, Visiting Lecturer, CAD/EDA course as part of MSc Digital Systems course. Member of external undergraduate advisory board.

Articles, papers, comments, press information relating to Simon Davidmann

General search: http://www.google.co.uk/search?q=%22simon+davidmann%22

General search: http://search.yahoo.com/search?p=%22simon+davidmann%22

General search: http://www.google.co.uk/search?q=%22simon+davidman%22

Search: http://www.eetimes.com/search/

Selected Published Articles, Papers, Interviews, etc in the last 4 years.

Aug 2002 - Interview by Drew Wilson – Speaking My Language - e-inSITE, www.e-insite.net/esec/Article_240036.htm

Aug 2002 - Synopsys makes $36M Acquisition –http://sanfrancisco.bizjournals.com/sanfrancisco/stories/2002/08/26/daily40.html

http://www.synopsys.com/news/announce/press2002/snps_codesign_pr.html

Jul 2002 – Article: Check the EDA Barometer – EETimes, http://www.eetimes.com/story/OEG20020724S0014

Jun 2002 – Co-Design’s Superlog donation becomes accepted as Accellera SystemVerilog 3.0 standard - http://www.electronicstimes.com/story/OEG20020606S0102

Nov 2001 - View from the Top – Interviews with CEOs -http://www10.dacafe.ibsystems.com/interview/

June 2001 - Interview on startups and focus - www.fastcompany.com/fast50/profile/?davidmann798

Sep 2000 - FDL 2001 - Conference Keynote Speech – Evolving the next design language - http://www.aifb.uni-karlsruhe.de/pipermail/ah/2000q3/000011.html

Jun 2000 – EETimes – Cooley eats humble pie - http://www.eetimes.com/story/OEG20001106S0024

Jun 2000 - Design Automation Conference Panel – the Future of System Design Languages, - http://portal.acm.org/citation.cfm?doid=337292.337533 http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac2000/papers/2000/dac00/pdffiles/25_panel.pdf

Apr 2000 – Paper IP 2000 Conference, Santa Clara - IP Re-Use requirements for System Level Design Languages

Mar 2000 – Article - The USE-Ability Metric for New Design Languages – Integrated System Design –- http://www.eedesign.com/editorial/2000/viewpoint0003.html

Mar 2000 - International HDL Conference Paper - SUPERLOG Evolving Verilog and C for System-On-Chip Design –

Nov 1999 - Article on unified language for HW/SW - Electronic News, www.e-insite.net/esec/Article_48409.htm

June 1999 – Coverage on company and SUPERLOG startup - http://www.techweb.com/wire/story/TWB19990601S0008

Participation in EDA Industry organisations

Member of Accellera Board of Directors – 1999-2002 – www.accellera.org

Member of Accellera committees: System Level Design Language, SystemVerilog 3.0, SystemVerilog Basic, Enhancement, Assertion, C interface committees - http://www.accellera.org/subcom.html

Member of various IEEE Verilog committees - http://www.verilog.com/IEEEVerilog.html

Member of UK ACM SigDA - http://infoeng.ee.ic.ac.uk/~gac1/SIGDA/members.htm