My current research, as an AI+EDA researcher at the University of Southampton, is on how AI applies to chip design and verification. Below it are my technical papers, the SystemVerilog book, granted patents and published applications, and my work on standards and open technical initiatives.
As design complexity grows, the bottleneck in verification has moved from simulation throughput to engineering cognition: the capacity to take in specifications, traces and coverage data. Introduces a taxonomy for AI in verification and reviews recent academic results in three areas: stimulus generation and coverage closure, test selection and bug triage, and performance prediction.
A survey of where AI and machine learning now meet EDA, prompted by the question asked at DAC 2025: are we living through the "Verilog moment" for AI? Covers commercial design verification products that use ML and AI, research in UK universities, how AI fits into chip verification workflows, and the shortage of appropriately licensed training data.
An invited paper for the fourth ACM History of Programming Languages conference (HOPL IV) on the history of Verilog, the languages that led to it, and the languages that followed it, including SystemVerilog.
A technique for adding timing information to instruction-accurate simulation of RISC-V processors, so fast virtual platforms can be used for timing estimation early in a project.
Covers the IEEE 1800-2005 SystemVerilog standard. Foreword by Phil Moorby.
Continuation of US 11,574,087: parallel, timesliced simulation of many processors on a multi-core host, with synchronisation handling.
Simulating many processors in parallel across the cores of a multi-core host. Each simulated processor runs in timeslices; processors that reach a synchronisation event are suspended and handled in order, so shared data stays consistent.
A processor simulator that translates code at run time and keeps a separate code dictionary for each processor mode, such as user, supervisor and hypervisor. A mode change switches dictionary, so the simulator does not test the mode on every instruction.
Simulating a multiprocessor system by translating the simulated processors' instructions. Shared-memory code regions are marked, and inside them a more detailed model of caches and coherence detects conflicting accesses between processors; outside them a faster model is used.
A hardware description language simulator that connects directly to C and C++. It maps data types, generates wrappers for function and task calls and handles threading, so HDL and C code can call each other without hand-written PLI code.
Verifying a processor design against an instruction-accurate reference model: keeping a mirror of the design's architectural state, handling implementation-defined state, exploring the allowed execution paths after asynchronous events such as interrupts, and re-converging after a divergence so verification can continue.
Simulating a chip or system by running its peripheral and behavioural models (C, C++, SystemC) on virtual processors inside the simulator, each with its own memory space, so models can be instantiated many times without interfering with each other.
Formed the US-based RAPID industry organisation to promote the silicon IP business, while at Virtual Chips
Co-architect of the Superlog language at Co-Design Automation. Worked with Accellera to make Superlog the basis of SystemVerilog 3.0, which became IEEE standard 1800.
Board member
Created and ran the OVPworld.org open initiative for processor models and virtual platform APIs
Member of many RISC-V technical working groups and committees
Chair
Developed the RVVI open standard while chairing the OpenHW Verification Task Group
Member of the System Level Design Language, SystemVerilog 3.0, SystemVerilog Basic, Enhancement, Assertion and C interface committees
Member of various IEEE Verilog committees