Writing & Talks
Articles I have written, interviews, articles that quote me, and talks, keynotes and panels from 1999 to today. Use the filters to narrow the list: "By me / about me" separates my own work from articles written about it.
Nothing matches these filters.
-
From AI-Assisted EDA to AI-Mediated Engineering
Reflections on DAC 2026, where agentic methods made up about 28% of the agenda and AI submissions had risen from under 300 in 2023 to about 700. Sets out the two technical routes, replacing the tool engines or wrapping them, and argues for evidence-grounded loops in which AI proposes and physics, formal methods or simulation decides.
-
Standards and AI will shape-shift EDA
Report on the Accellera panel at DAC 2026 on AI and standards in EDA, with quotes from the panel.
-
DAC 2026: Accellera Luncheon Panel on Embracing AI for Advanced Design and Verification
Mike Gianfagna's write-up of the Accellera luncheon panel at DAC 2026, which he moderated.
-
Harnessing AI for SoC Verification: Disruptive or Collaborative?
Panel on whether AI in SoC verification disrupts current flows or works alongside them.
-
Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas
Interview by Daniel Nenni on the move from Imperas and Synopsys to AI+EDA research at the University of Southampton. Covers how RISC-V users building AI accelerators led to this research, published results of ML in verification ranging from 85% less RTL simulation to 10% better coverage, Davidmann's Dilemma and Test, and why the larger opportunity for start-ups is a holistic rethink of the toolchain.
-
Embracing AI for Advanced Design and Verification
Accellera panel on how AI is changing design and verification, and what that means for EDA standards.
-
DAC 2026: Users Are Not Waiting; DIY AI Is Now in Vogue
Frank Schirrmeister's DAC 2026 report on chip design teams building their own AI flows, with reference to my framework and the Exhibitor Forum panel.
-
AI in EDA Is Real, It's Now, and It's on Show at DAC 2026
Frank Schirrmeister's preview of DAC 2026, built around two ideas from my work. Davidmann's Dilemma: "every camp acting rationally guarantees the collectively wrong outcome". Davidmann's Test: "Does it change what you can verify, or just how fast you run what you already verify?"
-
An AI Model Fit For Purpose
Quoted on judging AI models for EDA: accuracy has to separate syntactic correctness, functional correctness and formal completeness, and a model's reliability is bounded by the distribution of the data it was trained on.
-
Can AI Create Missing Models?
Quoted on using AI to create missing models: functional correctness and implementation correctness are different properties, and production use of AI-generated design content needs verification in the loop.
-
AI as a Cognitive Amplifier in Modern Design Verification
As design complexity grows, the bottleneck in verification has moved from simulation throughput to engineering cognition: the capacity to take in specifications, traces and coverage data. Introduces a taxonomy for AI in verification and reviews recent academic results in three areas: stimulus generation and coverage closure, test selection and bug triage, and performance prediction.
-
The next EDA wave: Lessons from DATE 2026
A review of DATE 2026 in Verona. AI now appears as a workload, a design tool, a research method and a security risk, and the move from single prompts to multi-agent, tool-grounded flows makes verification and security first-class constraints. Closes with the case for European capability in AI+EDA, built on its universities, its RISC-V community and its safety-critical industries.
-
Creating Agentic EDA Methodologies
Quoted on agentic EDA flows across many tools, vendors and data formats, and on companies with very large resources building their own AI solutions in-house.
-
CPU Processor Verification in the AI Era
Mike Bartley's summary of my DV Club Bristol talk on processor verification in the AI era.
-
The Magic of Agentic AI Will Come From a Holistic Approach to Chip Design
Interview on agentic AI in chip design. Most agentic tools today optimise existing flows; larger gains come from treating design, synthesis, verification and layout as one system, which some large technology companies already do in-house. New EDA start-ups aiming at step-function improvements need investors prepared to fund them.
-
A New Era For Co-Processing
Quoted on co-processor architectures for AI: the winning co-processor minimises data movement, software friction and verification risk at the same time.
-
What is the EDA problem worth solving with AI?
Most AI work in EDA speeds up what engineers already do. This article looks at the positions of the large EDA vendors, the agentic start-ups and the in-house teams at large chip companies, and proposes foundation models specialised with formal and domain structure, open APIs and serious collaboration between industry and universities.
-
Using Data And AI More Effectively In EDA
Quoted on the data available for AI in EDA: most of it is "human first", produced for engineers to read, and RVVI was built to give a trace that tools can interact with.
-
AI+EDA for DV Engineers
A survey of where AI and machine learning now meet EDA, prompted by the question asked at DAC 2025: are we living through the "Verilog moment" for AI? Covers commercial design verification products that use ML and AI, research in UK universities, how AI fits into chip verification workflows, and the shortage of appropriately licensed training data.
-
RISC-V Processor Verification Requires the Full Toolbox
Why RISC-V processor verification needs every technique available: dynamic verification, including test generation and hardware-assisted verification, and static and formal verification. Given as Synopsys VP Engineering, Processor Modeling and Verification.
-
RISC-V Micro-Architectural Verification
-
Synopsys Acquires RISC-V Processor Simulation Tools Firm
-
Generation and Configuration of Functional Coverage and Verification IP for RISC-V Processor Verification
With over 1,000 instructions in the RISC-V ISA, functional coverage for a fully featured processor can need more than 100,000 lines of SystemVerilog. Presents a methodology for generating the functional coverage modules automatically.
-
Solving the Conundrum of Custom Instructions
-
Delivering on RISC-V's Promise to Give Designers Freedom to Innovate: What's Needed?
-
RISC-V verification and implications of the 5:1 ratio of DV to design engineers
-
The RISC-V Verification Ecosystem with Open Standards and Commercial Tools
-
RISC-V Models for Verification, Software Development and Architectural Exploration
-
RISC-V Driving New Verification Concepts
-
Do Necessary Tools Exist For RISC-V Verification?
-
What Makes RISC-V Verification Unique?
-
Understanding the RISC-V Verification Ecosystem
-
Planning for RISC-V Success: Verification Planning and Functional Coverage lead to quality RISC-V processor IP
-
The Continuum of RISC-V Compliance and Verification Testing
-
Improving RISC-V Quality with Verification Standards and Advanced Methodologies
-
RISC-V processor verification with new open standard RVVI based methodology
-
Advancing RISC-V Processor Verification
-
The Art and Science of Automating Verification Checking
-
Introduction to the 5 Levels of RISC-V Processor Verification
-
Software Development for ML and RISC-V Vector Accelerators
-
RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV
-
A personal perspective on the history of SystemVerilog / Superlog
-
Verification in the Open-Source Era
-
RISC-V Verification Challenges Spread
-
Getting Started with RISC-V Verification
-
RISC-V & SoC Architectural Exploration for AI and ML Accelerators
-
Extending Cortex-M33 With Custom Instructions for Security Algorithms
-
Optimizing RISC-V Custom Instructions with Software Driven Analysis and Profiling
-
Verifying All the Flexibility of RISC-V within SoC DV Test Plans
-
Components For Open-Source Verification
-
Axiomise podcast with Ashish Darbari
-
RISC-V Compliance & Verification Techniques: Processor Cores and Custom Extensions
-
Avoiding Amdahl's Law: RISC-V Architecture Exploration for AI & ML Compute
-
How to Address RISC-V Compliance in the Era of Open ISA and Custom Instructions
-
A Common Software Development Environment for Many-core RISC-V based Hardware and Virtual Platforms
-
Software Verification for Low Power, Safety Critical Systems
-
Hardware virtualization for security
-
Virtual Platform Software Simulation for Enhanced Multi-core Software Verification
-
Maintaining Momentum When the Tide Turns
-
The Future of System Level Design
-
Speaking the Language of Reuse
-
Co-Design: A Question of Communication?
-
New Design Languages — Testing for USE-ability