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AI as a Cognitive Amplifier in Modern Design Verification
As design complexity grows, the bottleneck in verification has moved from simulation throughput to engineering cognition: the capacity to take in specifications, traces and coverage data. Introduces a taxonomy for AI in verification and reviews recent academic results in three areas: stimulus generation and coverage closure, test selection and bug triage, and performance prediction.
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CPU Processor Verification in the AI Era
Mike Bartley's summary of my DV Club Bristol talk on processor verification in the AI era.
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AI+EDA for DV Engineers
A survey of where AI and machine learning now meet EDA, prompted by the question asked at DAC 2025: are we living through the "Verilog moment" for AI? Covers commercial design verification products that use ML and AI, research in UK universities, how AI fits into chip verification workflows, and the shortage of appropriately licensed training data.
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Generation and Configuration of Functional Coverage and Verification IP for RISC-V Processor Verification
With over 1,000 instructions in the RISC-V ISA, functional coverage for a fully featured processor can need more than 100,000 lines of SystemVerilog. Presents a methodology for generating the functional coverage modules automatically.
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RISC-V processor verification with new open standard RVVI based methodology
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The Art and Science of Automating Verification Checking
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Software Verification for Low Power, Safety Critical Systems