Europe

12 May 2026 · EDN · Article · Author

The next EDA wave: Lessons from DATE 2026

A review of DATE 2026 in Verona. AI now appears as a workload, a design tool, a research method and a security risk, and the move from single prompts to multi-agent, tool-grounded flows makes verification and security first-class constraints. Closes with the case for European capability in AI+EDA, built on its universities, its RISC-V community and its safety-critical industries.

Republished

6 June 2023 · RISC-V Summit Europe 2023, Barcelona · Keynote · Keynote speaker

The RISC-V Verification Ecosystem with Open Standards and Commercial Tools

2023 · DVCon Europe 2023 · Talk · Co-speaker

Planning for RISC-V Success: Verification Planning and Functional Coverage lead to quality RISC-V processor IP

With: Aimee Sutton, Duncan Graham, Pascal Gouedo (Dolphin Design), Yoann Pruvost (Dolphin Design), Xavier Aubert (Dolphin Design)

Slides

October 2019 · DVCon Europe 2019, Munich · Tutorial · Speaker

RISC-V Compliance & Verification Techniques: Processor Cores and Custom Extensions

With: Lee Moore, Richard Ho (Google), Doug Letcher (Metrics Technologies), Kevin McDermott

Slides

July 2017 · Microprocessors and Microsystems, vol. 52, pp. 89–105 · Journal paper

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

M. Fakih, A. Lenz, M. Azkarate-Askasua, J. Coronel, A. Crespo, S. Davidmann, J.C. Diaz Garcia, N. González Romero, K. Grüttner, S. Schreiner, R. Seyyedi, R. Obermaisser, A. Maleki, J. Öberg, M.T. Mohammadat, J. Pérez-Cerrolaza, I. Sander, I. Söderquist

Open-access copyDOI

2016 · 2016 Euromicro Conference on Digital System Design (DSD), pp. 294–300 · Conference paper

SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems

A. Lenz, M. Azkarate-Askasua, J. Coronel, A. Crespo, S. Davidmann, J.C. Diaz Garcia, N. González Romero, K. Grüttner, R. Obermaisser, J. Öberg, J. Perez, I. Sander, I. Söderquist

DOI