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CPU Processor Verification in the AI Era
Mike Bartley's summary of my DV Club Bristol talk on processor verification in the AI era.
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AI+EDA for DV Engineers
A survey of where AI and machine learning now meet EDA, prompted by the question asked at DAC 2025: are we living through the "Verilog moment" for AI? Covers commercial design verification products that use ML and AI, research in UK universities, how AI fits into chip verification workflows, and the shortage of appropriately licensed training data.
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RISC-V Processor Verification Requires the Full Toolbox
Why RISC-V processor verification needs every technique available: dynamic verification, including test generation and hardware-assisted verification, and static and formal verification. Given as Synopsys VP Engineering, Processor Modeling and Verification.
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RISC-V Micro-Architectural Verification
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Generation and Configuration of Functional Coverage and Verification IP for RISC-V Processor Verification
With over 1,000 instructions in the RISC-V ISA, functional coverage for a fully featured processor can need more than 100,000 lines of SystemVerilog. Presents a methodology for generating the functional coverage modules automatically.
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Solving the Conundrum of Custom Instructions
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RISC-V verification and implications of the 5:1 ratio of DV to design engineers
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The RISC-V Verification Ecosystem with Open Standards and Commercial Tools
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RISC-V Driving New Verification Concepts
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Do Necessary Tools Exist For RISC-V Verification?
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What Makes RISC-V Verification Unique?
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Understanding the RISC-V Verification Ecosystem
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Planning for RISC-V Success: Verification Planning and Functional Coverage lead to quality RISC-V processor IP
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The Continuum of RISC-V Compliance and Verification Testing
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Improving RISC-V Quality with Verification Standards and Advanced Methodologies
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RISC-V processor verification with new open standard RVVI based methodology
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Advancing RISC-V Processor Verification
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The Art and Science of Automating Verification Checking
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Introduction to the 5 Levels of RISC-V Processor Verification
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RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV
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RISC-V Verification Challenges Spread
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Getting Started with RISC-V Verification
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Verifying All the Flexibility of RISC-V within SoC DV Test Plans
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Rolling the dice with random instructions is the safe bet on RISC-V verification