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Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas
Interview by Daniel Nenni on the move from Imperas and Synopsys to AI+EDA research at the University of Southampton. Covers how RISC-V users building AI accelerators led to this research, published results of ML in verification ranging from 85% less RTL simulation to 10% better coverage, Davidmann's Dilemma and Test, and why the larger opportunity for start-ups is a holistic rethink of the toolchain.
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A New Era For Co-Processing
Quoted on co-processor architectures for AI: the winning co-processor minimises data movement, software friction and verification risk at the same time.
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RISC-V Processor Verification Requires the Full Toolbox
Why RISC-V processor verification needs every technique available: dynamic verification, including test generation and hardware-assisted verification, and static and formal verification. Given as Synopsys VP Engineering, Processor Modeling and Verification.
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RISC-V Micro-Architectural Verification
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Synopsys Acquires RISC-V Processor Simulation Tools Firm
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Generation and Configuration of Functional Coverage and Verification IP for RISC-V Processor Verification
With over 1,000 instructions in the RISC-V ISA, functional coverage for a fully featured processor can need more than 100,000 lines of SystemVerilog. Presents a methodology for generating the functional coverage modules automatically.
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Solving the Conundrum of Custom Instructions
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Delivering on RISC-V's Promise to Give Designers Freedom to Innovate: What's Needed?
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RISC-V verification and implications of the 5:1 ratio of DV to design engineers
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The RISC-V Verification Ecosystem with Open Standards and Commercial Tools
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RISC-V Models for Verification, Software Development and Architectural Exploration
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RISC-V Driving New Verification Concepts
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Do Necessary Tools Exist For RISC-V Verification?
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What Makes RISC-V Verification Unique?
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Understanding the RISC-V Verification Ecosystem
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Planning for RISC-V Success: Verification Planning and Functional Coverage lead to quality RISC-V processor IP
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The Continuum of RISC-V Compliance and Verification Testing
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Improving RISC-V Quality with Verification Standards and Advanced Methodologies
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RISC-V processor verification with new open standard RVVI based methodology
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Advancing RISC-V Processor Verification
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Introduction to the 5 Levels of RISC-V Processor Verification
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Software Development for ML and RISC-V Vector Accelerators
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RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV
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RISC-V Verification Challenges Spread
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Getting Started with RISC-V Verification
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RISC-V & SoC Architectural Exploration for AI and ML Accelerators
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Optimizing RISC-V Custom Instructions with Software Driven Analysis and Profiling
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Verifying All the Flexibility of RISC-V within SoC DV Test Plans
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Components For Open-Source Verification
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Axiomise podcast with Ashish Darbari
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Rolling the dice with random instructions is the safe bet on RISC-V verification
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RISC-V Compliance & Verification Techniques: Processor Cores and Custom Extensions
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Avoiding Amdahl's Law: RISC-V Architecture Exploration for AI & ML Compute
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How to Address RISC-V Compliance in the Era of Open ISA and Custom Instructions
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A Common Software Development Environment for Many-core RISC-V based Hardware and Virtual Platforms
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Cycle Approximate Simulation of RISC-V Processors
A technique for adding timing information to instruction-accurate simulation of RISC-V processors, so fast virtual platforms can be used for timing estimation early in a project.