Simon Davidmann

History

The companies, languages, standards and products I have worked on since 1980, in date order. A summary of the technical contributions is on the History + technical contributions page.

HILO and early simulation

  1. 1975

    University of Essex

    BSc and MSc in Electronic Engineering.

  2. 1980

    HILO at Brunel University

    Research Fellow in the team that developed HILO, the first RTL simulation system.

    HILO-2: a system to build onHILO-2: A system to build on

  3. 1983

    To the US with HILO

    Moved to the US to sell and support HILO, marketed by GenRad.

Simmons electronic drums

  1. 1984

    Technical Director, Simmons

    Built the engineering department for processor-based electronic drums and percussion instruments.

  2. 1986

    SDS9 wins NAMM award

    The SDS9 won Most Innovative Product, Drums/Percussion, at the NAMM 1986 Music & Sound Awards.

Verilog and Gateway

  1. 1988

    Gateway Design Automation

    First European employee of the company that created Verilog.

  2. 1989

    Cadence acquires Gateway

  3. 1991

    EuCAD consulting, Cadence

    Business development for one of the first EDA consulting services groups.

VCS and Chronologic

  1. 1993

    Chronologic Simulation

    Set up European operations for the VCS Verilog simulator.

  2. 1994

    Viewlogic acquires Chronologic

  3. 1994

    Visiting Lecturer, King's College London

    Taught the CAD/EDA course on the MSc in Digital Systems until 1998, and served on the external undergraduate advisory board.

Silicon IP and synthesis

  1. 1995

    Virtual Chips

    Set up European operations for a pioneer of silicon IP, and formed the RAPID industry organisation.

    RAPID

  2. 1996

    Phoenix Technologies acquires Virtual Chips

  3. 1997

    Ambit Design Systems

    Set up European operations for timing-driven synthesis; Europe became the company's most successful region.

  4. 1998

    Cadence acquires Ambit for $280M

Superlog and SystemVerilog

  1. 1998

    Co-founded Co-Design Automation

    Co-architect of the Superlog language.

    Superlog and SystemVerilogSuperlog, a unified design language for system-on-chipMixed language simulator

  2. 1999

    Accellera Board of Directors

    Board member until 2002.

    Accellera Board of Directors

  3. 2002

    Synopsys acquires Co-Design for $36M

    Superlog became the basis of SystemVerilog 3.0 at Accellera.

    Superlog and SystemVerilog

  4. 2003

    SystemVerilog for Design

    Co-authored with Stuart Sutherland and Peter Flake. Second edition 2006.

    SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and ModelingSystemVerilog for Design, Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling

Imperas and virtual platforms

  1. 2004

    Visiting Professor, Queen Mary, University of London

    Centre for Digital Music, entrepreneurship and spin-outs, until 2014.

  2. 2005

    Founded Imperas

    Funded by Accel Partners and Pond Ventures.

    Multiprocessor development environmentProcessor simulation environment

  3. 2008

    Management buy-out and Open Virtual Platforms

    Refocused Imperas on processor and system modelling, and launched OVP.

    Open Virtual Platforms (OVP)

RISC-V processor verification

  1. 2015

    Imperas focuses on RISC-V

    RISC-V processor models and verification.

  2. 2020

    History of Verilog for ACM HOPL IV

    Verilog HDL and its ancestors and descendants

  3. 2022

    RVVI open standard

    Developed the RISC-V Verification Interface while chairing the OpenHW Verification Task Group.

    RISC-V Verification Interface (RVVI)OpenHW Verification Task Group

Synopsys

  1. December 2023

    Synopsys acquires Imperas

    Became Vice President Engineering, Processor Modeling and Verification.

    Computer-implemented methods of verifying a processor design under test, and related systemsSystem simulation using simulation models executing on virtual processors

  2. December 2025

    Left Synopsys

AI + EDA research

  1. AI+EDA Researcher, University of Southampton

    AI+EDA for DV EngineersAI as a Cognitive Amplifier in Modern Design VerificationWhat is the EDA problem worth solving with AI?

  2. July 2026

    DAC 2026 panels

    Accellera luncheon panel and Exhibitor Forum panel.

    Embracing AI for Advanced Design and VerificationHarnessing AI for SoC Verification: Disruptive or Collaborative?