History + technical contributions
The technical work I have been part of since 1980, most of it in simulation and verification:
- HILO (1980 to 1984). At Brunel University I was a Research Fellow in the small team that developed HILO, the first RTL simulation system. HILO was marketed by GenRad, and in 1983 I moved to the US to sell and support it.
- Verilog (1988 to 1991). I was the first European employee of Gateway Design Automation, the company that created Verilog, and later worked on product development in the US after Cadence acquired it.
- VCS (1993 to 1995). Chronologic Simulation developed VCS, the leading Verilog simulator of the 1990s. I set up and ran its European operations.
- Silicon IP and synthesis (1995 to 1998). At Virtual Chips I helped build the business of soft silicon IP and formed the RAPID industry organisation to promote it. At Ambit I set up European operations for timing-driven logic synthesis.
- Superlog and SystemVerilog (1998 to 2005). At Co-Design Automation, which I co-founded with Peter Flake, we created Superlog as a superset of Verilog. Through Accellera it became SystemVerilog 3.0, and then IEEE standard 1800. I co-wrote SystemVerilog for Design with Stuart Sutherland and Peter Flake.
- Virtual platforms (2005 onwards). Imperas built fast processor models and simulators, and in 2008 launched Open Virtual Platforms (OVP) as an open initiative.
- RISC-V verification (2015 to 2025). Imperas moved into RISC-V processor verification, developing the RVVI open standard. I continued this work at Synopsys until December 2025.
In 2020 I co-wrote, with Peter Flake, Phil Moorby, Steve Golson and Arturo Salz, the history of Verilog for the ACM History of Programming Languages conference (HOPL IV).
The full timeline, company by company, is on the History page.
Writing & Talks
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28 July 2026 · SemiWiki, Daniel Nenni · Interview · Interviewed
Interview by Daniel Nenni on the move from Imperas and Synopsys to AI+EDA research at the University of Southampton. Covers how RISC-V users building AI accelerators led to this research, published results of ML in verification ranging from 85% less RTL simulation to 10% better coverage, Davidmann's Dilemma and Test, and why the larger opportunity for start-ups is a holistic rethink of the toolchain.
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21 December 2023 · EE Times, Nitin Dahad · Report · Featured
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2 March 2021 · DVCon US 2021, Virtual · Session · Host
With: Phil Moorby, Peter Flake
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10 June 2002 · EDN · Article · Author
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8 January 2001 · EDN · Article · Author
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15 May 2000 · EDN · Article · Author
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22 November 1999 · EDN · Article · Author
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21 June 1999 · EDN · Article · Author
Papers
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June 2020 · Proceedings of the ACM on Programming Languages, vol. 4, HOPL IV, article 87, pp. 1–90 · Journal paper
Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon Davidmann
An invited paper for the fourth ACM History of Programming Languages conference (HOPL IV) on the history of Verilog, the languages that led to it, and the languages that followed it, including SystemVerilog.
ProgrammeDOI
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2006 · 43rd Design Automation Conference (DAC 2006), p. 286 · Conference paper
Peter Flake, Simon Davidmann, Frank Schirrmeister
DOI
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2000 · Asia and South Pacific Design Automation Conference (ASP-DAC 2000), pp. 583–586 · Conference paper
Peter L. Flake, Simon J. Davidmann
DOI
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March 1984 · Computer-Aided Design, vol. 16, no. 2 · Journal paper
R.L. Harris, S.J. Davidmann, G. Musgrave
DOI
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1984 · CAD84 conference proceedings, pp. 48–60 · Book chapter
R.L. Harris, S.J. Davidmann, G. Musgrave
DOI
Granted patents
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US 7,035,781 B1
Inventors: Peter Flake, Simon Davidmann, Matthew Hall, James Kenney
Priority date 30 December 1999Filed 29 December 2000Granted 25 April 2006
A hardware description language simulator that connects directly to C and C++. It maps data types, generates wrappers for function and task calls and handles threading, so HDL and C code can call each other without hand-written PLI code.