Simon Davidmann

Verification + RISC-V

For most of the history of the processor IP business, a processor core came from a single vendor as known-good IP, verified by that vendor. With RISC-V, the situation is different. Every SoC team can design its own processor or extend an existing one, and every such team then has to verify it. Processor verification, once the concern of a few specialist companies, has become a problem for the whole industry.

Work at Imperas

From 2015 Imperas focused on RISC-V processor models and verification. The approach we developed, ImperasDV, uses an instruction-accurate reference model running in lock-step with the processor design under test, comparing the two instruction by instruction, including after asynchronous events such as interrupts. Synopsys acquired Imperas in 2023.

Related work:

Verification needs the full toolbox

RISC-V processor verification needs every technique available: random and directed test generation, reference-model comparison, functional coverage, hardware-assisted verification, and static and formal methods. I set this out at Verification Futures UK in 2025. The number of design verification engineers needed per design engineer, often quoted at around five to one, is one reason AI is now being applied to verification. That link is the subject of my current AI + EDA research.

Questions I am exploring

Writing & Talks

Papers

Granted patents